each pll has two multipliers/dividers
	Fout = 14.7456 * (PLL1_X1FBD + 1) * (PLL1_X2FBD + 1) /
					(PLL1_X2IPD + 1) / 2 ^ PLL1_PS

FCLK = processor clock
HCLK = AHB bus clock
PCLK = APB bus clock

FCLK >= HCLK > PCLK

FCLK <= 200 MHz
HCLK <= 100 MHz
PCLK <= 50 MHz

FCLK = PLL1 / FCLKDIV (1,2,4,8,16)
HCLK = PLL1 / HCLKDIV (1,2,4,5,6,8,16,32)
PCLK = HCLK / PCLKDIV (1,2,4,8)

for a 400.05 MHz PLL1 clock (f.e. ClkSet1 = 02A4BB36), we can have:

FCLK(DIV)			HCLK(DIV)	PCLK(DIV)	word
200(2), 100(4)			100(4)		50(2)		0[24]A4BB36
200(2), 100(4)			100(4)		25(4)		0[24]A8BB36
200(2), 100(4)			100(4)		12.5(8)		0[24]ACBB36
200(2), 100(4)			80(5)		40(2)		0[24]B4BB36
200(2), 100(4)			80(5)		20(4)		0[24]B8BB36
200(2), 100(4)			80(5)		10(8)		0[24]BCBB36
200(2), 100(4)			66.6(6)		33.3(2)		0[24]C4BB36
200(2), 100(4)			66.6(6)		16.6(4)		0[24]C8BB36
200(2), 100(4)			66.6(6)		8.3(8)		0[24]CCBB36
200(2), 100(4), 50(8)		50(8)		25(2)		0[246]D4BB36
200(2), 100(4), 50(8)		50(8)		12.5(4)		0[246]D8BB36
200(2), 100(4), 50(8)		50(8)		6.25(8)		0[246]DCBB36
200(2), 100(4), 50(8), 25(16)	25(16)		12.5(2)		0[2468]E4BB36
200(2), 100(4), 50(8), 25(16)	25(16)		6.25(4)		0[2468]E8BB36
200(2), 100(4), 50(8), 25(16)	25(16)		3.125(8)	0[2468]ECBB36
200(2), 100(4), 50(8), 25(16)	12.5(32)	6.25(2)		0[2468]F4BB36
200(2), 100(4), 50(8), 25(16)	12.5(32)	3.125(4)	0[2468]F8BB36
200(2), 100(4), 50(8), 25(16)	12.5(32)	1.5625(8)	0[2468]FCBB36

watchdog: static 32 kHz oscillator
peripherals: 14.7456 MHz directly
CPU and bus clocks: PLL1 or 14 MHz
USB and FIR clocks: PLL2
video clock: PLL1, PLL2 or 14.7456 MHz
audio clocks: PLL1, PLL2 or 14.7456 MHz
MIR clock: PLL1, PLL2 or 14.7456 MHz
key touch clock: 14.7456 MHz


NOTE ethernet PHY clock is derived from HCLK !!!!




PwrSts = 4320ABD3

WDTFLG = 1
RSVD = 0
CLDFLG = 1
TEST_RESET = 0
RSTFLG = 1
SW_RESET = 0
PLL2_LOCK_REG = 1
PLL2_LOCK = 1
PLL1_LOCK_REG = 1
PLL1_LOCK = 1
RTCDIV = 010011


ClkSet1 = 02A4BB36

FCLK_DIV = 001 (div by 2)
SMC_ROM = 0
nBYP1 = 1
HCLK_DIV = 010 (div by 4)
PCLK_DIV = 01 (div by 2)
PLL1_PS = 00 (div by 1)
PLL1_X1FBD1 = 10111 (24)
PLL1_X2FBD2 = 011001 (26)
PLL1 X2IPD = 10110 (23)

	=> PLL1 Fout = 14.7456 * 24 * 26 / 23 = 400.05 MHz
		FCLK = 400.05 / 2 = 200.02 MHz
		HCLK = 400.05 / 4 = 100.01 MHz
		PCLK = 100.01 / 2 = 50.00 MHz


ClkSet2 = 300DC317

USB DIV = 0011 (div by 4)
RSVD = 00000000
nBYP2 = 1 (not bypassed)
PLL2_EN = 1 (enabled)
PLL2_PS = 01 (div by 2)
PLL2 X1FBD1 = 11000 (25)
PLL2 X2FBD2 = 011000 (25)
PLL2 X2IPD = 10111 (24)

	=> PLL2 Fout = 14.7456 * 25 * 25 / 24 / 2 = 192 MHz
		USB CLK = 192 / 4 = 48 MHz


DeviceCfg = 08940D00